[24屆]數(shù)字電路設(shè)計(jì)工程師 (職位編號(hào)：tsmcnj000575)
面議
應(yīng)屆畢業(yè)生
學(xué)歷不限
應(yīng)屆畢業(yè)生
學(xué)歷不限
- 全勤獎(jiǎng)
- 節(jié)日福利
- 不加班
- 周末雙休
最近更新
10591人關(guān)注
職位描述
該職位還未進(jìn)行加V認(rèn)證，請(qǐng)仔細(xì)了解后再進(jìn)行投遞！
崗位職責(zé):
1.Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)
2.Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective)
任職要求:
1.Good knowledge of circuits design. Experience in digital circuit or analog design is preferred.
2.Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred
3.CAD and script capability such as Python/Perl/Shell is preferred.
4.Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.
5.Experience in reliability (EM, high-temperature aging effects, etc.) is a plus
6.Self-motivated and hard work.
1.Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)
2.Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective)
任職要求:
1.Good knowledge of circuits design. Experience in digital circuit or analog design is preferred.
2.Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred
3.CAD and script capability such as Python/Perl/Shell is preferred.
4.Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.
5.Experience in reliability (EM, high-temperature aging effects, etc.) is a plus
6.Self-motivated and hard work.
注：聯(lián)系我時(shí)，請(qǐng)說是在應(yīng)城人才網(wǎng)上看到的。
工作地點(diǎn)
地址：漯河郾城區(qū)九龍湖國際企業(yè)總部
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職位發(fā)布者
HR
臺(tái)積電(南京)有限公司
-
電子技術(shù)·半導(dǎo)體·集成電路
-
200-499人
-
外商獨(dú)資·外企辦事處
-
浦口經(jīng)濟(jì)開發(fā)區(qū)紫峰路16號(hào)
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